1. Field of the Invention
The present invention relates to a method for reading a nonvolatile memory device and to a nonvolatile memory device implementing the reading method.
2. Discussion of the Related Art
As is known, in nonvolatile memory cells of the floating-gate type, a logic state is stored by programming the threshold voltage of the memory cells through the definition of the amount of electrical charge stored in the floating-gate region.
Thanks to the evolution of technological processes, allowing the implementation of elementary memory devices of increasingly smaller size, in the last few years semiconductor memory devices having very high memory capacities have been obtained. A further increase in the memory capacity has been obtained by resorting to multilevel storage, which enables an increase in the memory density for the same technological generation. In fact, with this technique, more information bits are stored within a individual memory cell normally used for containing just one bit.
Although based on the same principle, writing and reading of memory cells capable of storing just one bit (two-level memory cells) and of memory cells capable of storing more than one bit (multilevel memory cells) are performed according to different modalities.
In particular, according to the information stored, two-level memory cells are distinguished between erased memory cells (logic value stored “1”), wherein the floating-gate region does not store any electrical charge, and written or programmed memory cells (logic value stored “0”), wherein the floating-gate region stores an electrical charge sufficient for determining a sensible increase in the threshold voltage of the memory cells.
Reading of two-level memory cells is performed by comparing an electrical quantity correlated to the current flowing through the memory cells with a similar electrical quantity correlated to the current flowing through a reference memory cell of known contents. In particular, to read a two-level memory cell, the gate terminal of the memory cell is fed with a reading voltage having a value comprised between the threshold voltage of an erased memory cell and the threshold voltage of a written memory cell, so that, if the memory cell is written, the reading voltage is lower than its threshold voltage and consequently no current flows in the memory cell, while if the memory cell is erased, the reading voltage is higher than its threshold voltage and current flows in the cell.
In multilevel memory cells, storage of n-bit data requires, instead, programming of threshold voltages that may assume 2n different values, each associated with a respective n-bit datum, while reading of multilevel memory cells is performed by comparing an electrical quantity correlated to the current flowing through the memory cells with 2n distinct reference intervals (defined by 2n−1 distinct reference levels), each associated with a respective n-bit datum, and then by determining the datum associated with the range of values within which the electrical quantity is comprised.
The multilevel approach may be applied both to volatile memories (such as DRAMs) and to nonvolatile memories (such as EEPROMs and flash memories). In any case, the increase in the number of bits per memory cell renders more critical the tolerance to disturbance, retention of information, and accuracy of reading and writing operations.
FIG. 1 shows, for example, a graph representing the current flowing [(I[μA]), (0–70 μA)] in a multilevel memory cell storing two bits and the reference currents defining reference intervals used for reading the contents of the memory cell.
In particular, FIG. 1 shows with dashed line the current ICELL flowing in a memory cell storing the bits “10”, and a solid line represents the three reference currents IREF1, IREF2, IREF3 that define the four reference intervals. FIG. 1 also represents the two bits associated with each of the four reference intervals and, with a dashed-and-dotted line, the current flowing in a virgin cell, which, as known, is higher than the highest reference current (IREF3).
It is likewise known that reading of a memory cell is performed by a read circuit generally known as “sense amplifier” (also used hereinafter), which, in addition to recognizing the logic state stored in the memory cell, also provides for correct biasing of the drain terminal of the memory cell.
Basically, two types of sense amplifiers are used for reading multilevel memory cells: sense amplifiers of so-called parallel or flash type, and sense amplifiers of so-called synchronous-serial-dichotomic or successive-approximations type.
FIG. 2 illustrates, by way of example, the circuit architecture of a known sense amplifier of parallel type for reading a two-bit memory cell.
In particular, in sense amplifiers of parallel type, reading of the contents of the memory cell is performed by comparing the cell current ICELL simultaneously with the three reference currents IREF1, IREF2, IREF3 using three distinct comparator stages operating in parallel, one for each reference current, the outputs whereof are connected to a decoding stage supplying the two bits stored in the memory cell to be read according to the logic level assumed by the outputs of the comparator stages.
FIG. 3, instead, shows the dichotomic algorithm implemented by sense amplifiers of synchronous-serial-dichotomic type for reading the contents of a multilevel memory cell storing two bits, while FIG. 4 illustrates the circuit architecture of a known sense amplifier of a synchronous-serial-dichotomic type.
In particular, as illustrated in FIG. 3, in sense amplifiers of synchronous-serial-dichotomic type, reading of the contents of the memory cell, in the example shown consisting again of the bits “10”, is performed in two temporally consecutive steps, referred to as dichotomic steps, one for each of the two bits to be read, wherein in the first dichotomic step the current ICELL flowing in the memory cell is compared with the reference current IREF2, the value whereof is intermediate between the values assumed by the other reference currents, while in the second dichotomic step the current ICELL flowing in the memory cell is compared with the reference current IREF1 or IREF3 according to the outcome of the comparison performed in the first dichotomic step. In particular, if in the first dichotomic step the current ICELL is higher than the reference current IREF2, then in the second dichotomic step the current ICELL is compared with the reference current IREF3, while if in the first dichotomic step the current ICELL is lower than the reference current IREF2, then in the second dichotomic step the current ICELL is compared with the reference current IREF1.
In each dichotomic step, one of the two bits is then decoded; in particular, in the first dichotomic step the most significant bit (MSB) is decoded, while in the second dichotomic step the least significant bit (LSB) is decoded.
As shown in FIG. 4, in sense amplifiers of synchronous-serial-dichotomic type, reading of the contents of the memory cell is performed using a single comparator stage which, in the first dichotomic step, compares the cell current ICELL with the reference current IREF2, and, in the second dichotomic step, compares the current ICELL with the reference current IREF1 or IREF3 according to the outcome of the comparison in the first dichotomic step.
In particular, the selection of the reference current IREF1, IREF2, IREF3 to be compared with the cell current ICELL is performed through a multiplexer stage controlled by a control circuit, which is also connected to two registers or latches storing the two bits read.
Although widely used, sense amplifiers of parallel type and sense amplifiers of synchronous-serial-dichotomic type have a number of drawbacks that do not enable an adequate exploitation of all their qualities.
First, both sense amplifiers of parallel type and sense amplifiers of synchronous-serial-dichotomic type are very bulky.
In fact, sense amplifiers of parallel type require a comparator stage for each of the bits stored in the memory cells, which, as is known, occupies a non-negligible area, so that the use of this type of sense amplifier becomes in effect disadvantageous as the number of bits stored in the memory cells increases.
Sense amplifiers of synchronous-serial-dichotomic type, although using just one comparator stage, require registers for storing the bits read in each dichotomic step, a multiplexer stage, and a control stage. In addition, this type of sense amplifier requires an accurate management of the various dichotomic steps so that the circuit complexity of the control stage, and hence its bulk, increases significantly as the number of bits stored in the memory cells increases.
In addition, in sense amplifiers of synchronous-serial-dichotomic type, all the various dichotomic steps have a same temporal duration which is established a priori for the so-called worst case, i.e., to enable reliable reading of a bit even in case of simultaneous occurrence of all the operating conditions that determine a slowing-down of reading (low supply voltage, high capacitances to be charged/discharged, etc.); furthermore the dichotomic steps are synchronized with each other, i.e., a dichotomic step starts after a pre-set time interval from the start of the previous dichotomic step, irrespective when the first comparator stage has actually terminated the comparison between the cell current ICELL and the reference current IREF2.
For the above reasons, the reading speed of synchronous-serial-dichotomic sense amplifiers is not very high; in particular, the total time for reading the contents of a nonvolatile memory cell has on average, in this type of sense amplifier, rather high values of the order of 20–25 ns, which, in some applications, is not acceptable.
To trade off, in a better way as compared to the sense amplifiers described above, the contrasting needs of small area and high reading speed, U.S. patent application Ser. No. 10/118,660, filed Apr. 8, 2002, published as US2002/0186592, which is incorporated herein by reference, teaches a sense amplifier of the asynchronous-serial-dichotomic type, the circuit architecture whereof is illustrated in FIG. 5 in the case of reading of two-bit memory cells.
In particular, the sense amplifier is basically made up of a first and a second comparator, and a two-way multiplexer for selecting the reference current with which the cell current must be compared in the second dichotomic step.
Reading of the contents of the memory cell is performed in two dichotomic steps similarly to what described previously with reference to sense amplifiers of the synchronous-serial-dichotomic type, except that the two dichotomic steps are asynchronous to each other.
In particular, in the first dichotomic step, the cell current ICELL is compared with the reference current IREF2, while in the second dichotomic step, the cell current ICELL is compared with the reference current IREF1 if the cell current ICELL is lower than the reference current IREF2, or with the reference current IREF3 if the cell current ICELL is higher than the reference current IREF2.
One of the two bits is decoded in each dichotomic step; in particular, in the first dichotomic step the most significant bit (MSB) is decoded, while in the second dichotomic step the least significant bit (LSB) is decoded.
In addition, the second dichotomic step starts as soon as the comparison between the cell current ICELL and the reference current IREF2 is terminated, contrary to sense amplifiers of the synchronous-serial-dichotomic type wherein, due to the duration of each dichotomic step being established a priori for the worst case, the second dichotomic step starts after a preset time interval from the start of the first dichotomic step, irrespective of when the first comparator stage has terminated the comparison between the cell current ICELL and the reference current IREF2.
This enables a significant reduction in the reading time as compared to the sense amplifiers of the synchronous-serial-dichotomic type. In fact, the average time for reading the contents of a two-bit memory cell is reduced from 70 ns of a synchronous-serial-dichotomic sense amplifier to 50 ns. It can thus be immediately understood how the benefits in terms of reduction of the reading time become increasingly more significant, as compared to synchronous-serial-dichotomic sense amplifiers, the higher the number of bits stored in the memory cells.
Not only, but an asynchronous configuration, using a comparator stage for each dichotomic step, also enables saving of silicon area, which, in a synchronous configuration, is occupied by the control circuit and by the registers.
Notwithstanding the considerable improvements achieved, reading of multilevel memory cells continues in any case in general to be afflicted by a series of problems linked essentially to the intrinsic characteristics of the memory device in general and of the memory cells in particular.
A first of such problems is, for example, represented by the so-called apparent displacement of the distributions of the threshold voltages of the memory cells caused by the datum to be read.
In particular, it has been verified that in multilevel memory cells the outcome of reading a datum stored in a block of memory cells belonging to a same sector may also depend, to a non-negligible extent, upon the datum itself; i.e., the reading of the contents of a given memory cell is influenced by the reading of the contents of the adjacent memory cells, and this influence is particularly significant in multilevel memory cells, so much so as possibly to lead to reading errors.
As known, in fact, in nonvolatile memory devices, the memory array is generally divided into sectors, each of which is made up of a group of memory cells having source terminals connected to a common node to enable reading and programming of individual memory cells of the sector and simultaneous erasing of all the memory cells of the sector.
With this architecture, the voltage on the common node connected to the source terminals of all the memory cells belonging to a same sector depends upon the current drained by the memory cells being read, so that, given that the outcome of the reading of the contents of a memory cell depends to a significant extent upon the voltage present on its own source terminal, the variation that the voltage present on the common node can undergo according to the datum that is being read may lead to errors in reading the contents of a memory cell.
A further problem is linked to the way the references necessary for reading are generated.
In particular, in order to prevent any mismatch between the sense amplifiers, two architectures for generation of the references are used alternatively: a centralized one and a local one.
The centralized reference-generation architecture, illustrated schematically in FIG. 6 in the case of multilevel memory cells that store two bits, envisages basically that the three reference currents supplied to each of the sense amplifiers are obtained by mirroring an equal number of reference currents generated by a suitable reference generating circuit. This solution, albeit with the minor generation errors, entails, however, the use of current mirrors made up of transistors of rather large size, so that this solution has the biggest bulk and a current consumption proportional to the size of the transistors for charging the capacitances associated to their gate regions.
The local reference-generation architecture, illustrated schematically in FIG. 7 once again for the case of multilevel memory cells storing two bits, basically envisages that the three reference currents supplied to each of the sense amplifiers are directly generated by the reference generating circuit. This solution, albeit having a smaller bulk in so far as it does not entail current-mirror transistors, leads, however, during testing of the memory device, to long times for checking the references generated.
A further problem that adversely affects reading of multilevel memory cells is represented by the so-called “bending” of the voltage-current characteristics of the memory cells, this bending being in turn originated by the so-called “column path” created by the current of the memory cells being read.
In particular, in FIG. 8, a dashed line illustrates the ideal voltage-current characteristic of a memory cell, while a solid line illustrates the actual voltage-current characteristic of a memory cell, which has an evident bending downwards for high cell currents, being caused by the voltage drops on the column-selection transistors and possibly leading to an evident adverse effect on reading.
In order to minimize the voltage drops on the selection transistors, it is necessary for them to be very conductive, i.e., present a low electrical resistance, and this may be obtained only by using transistors of large size, which obviously occupy a large amount of silicon area.
The reading of multilevel memory cells is then strongly influenced by the precision and by the repeatability of the reading voltage supplied to the gate terminals of the memory cells during successive reading operations, the precision and repeatability depending to a marked extent upon the presence of ripple on the reading voltage (VREAD), the variation of the operating temperature of the memory device, the variation of the supply voltage supplied from outside the memory device, and any excessively close memory accesses.
Finally, reading of multilevel memory cells is also influenced by the gain spread of the memory cells due to process spreads, by the widening of the distributions of the drain currents ID caused by the gain variation of the multilevel memory cells, which is in turn caused by variations in the operating temperature (T1 T2) of the memory device, as shown in FIG. 9, and by the compression of the distributions of the drain currents ID of the multilevel memory cells caused by minimum-gain memory cells, as highlighted in FIG. 10.